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叶擦写PLD(EPLD)的设计往往会受到其有效输出脚的数目限制。当许多多位信号来自同一个器件时,这种局限性尤其如此。N位信号及其数据选通脉冲采取N+1个输出脚。这种输出脚的数目与EPLD逻辑的复杂性相比,
Erase-write PLD (EPLD) designs are often limited by the number of their effective output pins. This is especially true when many multi-bit signals come from the same device. The N-bit signal and its data strobe take N + 1 output pins. The number of such output pins compared with the complexity of EPLD logic,